The area of advanced gate dielectrics has gained considerable attention recently, because technology roadmaps predict the need for a sub-2.0 nanometer SiO2 gate dielectric for sub-0.13 micron complementary metal-oxide-semiconductor (CMOS) technology. There are leakage current and reliability concerns, however, for SiO2 in this thickness regime.
In response to the need to find replacements for SiO2, different materials are being evaluated as possible substitutes for SiO2 as a gate dielectric material. For example, HfSixOy and ZrSixOy are two of the promising high-κ gate dielectric candidates which are expected to meet the need for sub 2.0 nanometer gate dielectrics for sub-0.13 micron scaled silicon CMOS. However, the stability of the (HfSixOy, ZrSixOy)/silicon interface following dopant activation annealing remains one of the most important issues to be resolved. Dopant activation annealing for short durations (<30 sec) at 1050° C. can result in undesirable properties, including: interfacial layer growth, microstructural changes in the film, and possible metal outdiffusion from the gate dielectric into the transistor channel region. Metal incorporation into the channel region is likely to affect the electrical behavior of silicon-based CMOS transistors, since it is well known that CMOS device performance is sensitive to impurities in the channel region of the transistor. Substantial metal (Zr or Hf) incorporation into the channel region of the transistor is expected to decrease the electrical performance of silicon-based CMOS transistors, mostly due to deleterious effects on carrier mobility.
Embodiments of the invention address the above problem and other problems.